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ISL8200M
3.5
3.0
12
10
2.5
2.0
1.5
1.0
0.8V
1.5V
3.3V
8
6
4
3.3V
1.5V
0.8V
0.5
2
0.0
0
2
4
6
8
10
0
60
70
80
90
100
110
LOAD CURRENT (A)
FIGURE 29. POWER LOSS vs LOAD CURRENT (5V IN )
5.0
12
AMBIENT TEMPERATURE (°C)
FIGURE 30. DERATING CURVE (5V IN )
4.5
4.0
5.0V
10
3.5
3.0
2.5
2.0
1.5
0.8V
1.5V
2.5V
3.3V
8
6
4
5.0V
3.3V
2.5V
1.5V
0.8V
1.0
0.5
2
0.0
0
2
4
6
8
10
0
60
70
80
90
100
110
LOAD CURRENT (A)
FIGURE 31. POWER LOSS vs LOAD CURRENT (12V IN )
Thermal Considerations
Experimental power loss curves along with θ JA from
thermal modeling analysis can be used to evaluate the
thermal consideration for the module. The derating
curves are derived from the maximum power allowed
while maintaining the temperature below the maximum
junction temperature of +125°C. In actual application,
other heat sources and design margin should be
considered.
Package Description
The structure of ISL8200M belongs to the Quad Flat-
pack No-lead package (QFN). This kind of package has
advantages, such as good thermal and electrical
conductivity, low weight and small size. The QFN
package is applicable for surface mounting technology
and is being more readily used in the industry. The
ISL8200M contains several types of devices, including
resistors, capacitors, inductors and control ICs. The
ISL8200M is a copper lead-frame based package with
exposed copper thermal pads, which have good
electrical and thermal conductivity. The copper lead
frame and multi component assembly is overmolded
with polymer mold compound to protect these devices.
19
AMBIENT TEMPERATURE (°C)
FIGURE 32. DERATING CURVE (12V IN )
The package outline and typical PCB layout pattern
design and typical stencil pattern design are shown in the
package outline drawing L23.15x15 on page 22. The
module has a small size of 15mm x 15mm x 2.2mm.
Figure 33 shows typical reflow profile parameters. These
guidelines are general design rules. Users could modify
parameters according to their application.
PCB Layout Pattern Design
The bottom of ISL8200M is a lead-frame footprint, which
is attached to the PCB by surface mounting process. The
PCB layout pattern is shown in the Package Outline
Drawing L23.15x15 on page 22. The PCB layout pattern
is essentially 1:1 with the QFN exposed pad and I/O
termination dimensions, except for the PCB lands being a
slightly extended distance of 0.2mm (0.4mm max)
longer than the QFN terminations, which allows for solder
filleting around the periphery of the package. This
ensures a more complete and inspectable solder joint.
The thermal lands on the PCB layout should match 1:1
with the package exposed die pads.
FN6727.1
February 26, 2010
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